The present invention is directed to a semiconductor integrated circuit device and to the method of its fabrication; and, more particularly, the invention is directed to a technology that is effective for application to semiconductor integrated circuit devices with low levels of current consumption, such as a SRAM (static random access memory).
An SRAM with memory cells composed of six MISFETs is used in a cache memory for personal computers or workstations.
An SRAM is composed of a flip-flop circuit that stores one bit of data and of two MISFETs (metal insulator semiconductor field effect transistors) for the transfer of data. The flip-flop circuit is configured, for example, as a pair of driver MISFETs and a pair of load MISFETs.
In these MISFETs, a silicide layer is formed on the source/drain regions to decrease the resistance of the source/drain region and to decrease the contact resistance between the source/drain and a plug that is subsequently to be formed on the source/drain region. At the same time, in these MISFETs, a silicide layer is also formed on the gate electrode to decrease the resistance of the gate electrode (gate wiring).
This silicide layer is formed by depositing a metal layer on the source/drain regions and on the gate electrode and then causing silicidation in the part where the source/drain regions (silicon substrate) and the metal layer come into contact and in the part where the gate electrode (silicon layer) and the metal layer come into contact.
At this time, a technique for etching out the natural oxide on the source/drain regions (silicon substrate) and the gate electrode (silicon layer) prior to deposition of the metal is employed to avoid the agglomeration of silicide. As intended, this keeps the silicide's sheet resistance low.
For example, the Hei. 9-320987 issue of the Patent Laid-Open Official Gazette discloses a technique in which approximately 3 nm to 5 nm is etched away from the surface of a silicon substrate, and then a metal film is deposited and thermally processed to form a silicide layer.
In addition, the Hei. 7-161660 issue of the Patent Laid-Open Official Gazette discloses a technique in which a natural oxide film is removed from the surface of both a silicon substrate and gate polycrystalline silicon by sputter etching using ions of an inert gas, and a Ti film is deposited to form Ti silicide film through thermal processing.